After that the decoder outputs the wrong value that it is suppose to display. When I run the program it outputs the correct output until it reaches the test case where the input is 1101. 4.23 Draw the logic diagram of a 2-to-4-line decoder using (a) NOR gates only and. #85 $display("select = %b \t out = %b", select, out) (b) List the truth table with 16 binary combinations of the four input. Here is the code for the Decoder and test, and the output at the console:Ĥx16 Decoder: module Decoder4x16 (input select, input enable, output reg out) ĭecoder4x16 decoder(select, enable, out) I can't manage to get all the desired outputs when I run the program. For each case the decoder should output a 16-bit digit with only one of the bits high. ![]() I have implemented a 4x16 Decoder using Verilog along with it's test. Decoders are used to decode data that has been previously encoded using a binary, or possibly other, type of coded format.
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